Thursday, November 14, 2019
 

Designing Electronic Systems for Future Applications

14:30 Welcome
  Bob Smith, Executive Director at Electronic System Design Alliance
14:40
Next Generation SoC Design: From Atoms to Systems
  Babak Taheri, CEO/CTO of Silvaco, Silvaco Inc
Next Generation SoC Design: From Atoms to Systems
Babak Taheri

Babak Taheri
CEO/CTO of Silvaco
Silvaco Inc

Babak Taheri

Abstract
Integrating the most advanced nanometer technologies such as FinFETs, Quantum Dots, MicroLEDs, MRAM, and ReRAM in IP and SoC designs, requires new simulation, optimization, and automation technologies. Physical models for new materials need to be captured to enable TCAD process and device simulation that extends from the atomic-level to the circuit-level. This simulation and modeling can then be promoted to a higher level for design and technology co-optimization (DTCO) from device to IP level, followed by system and technology co-optimization at the SoC level. Silvaco TCAD software accurately simulates the manufacturing process, device characteristics and resulting circuity. In addition, Silvaco EDA tools take the results of TCAD analysis to simulate circuit behavior across a range of effects including process, voltage and temperature variability, and enable a cohesive DTCO flow for Smart Design. In this talk, I will describe the need for a toolset that can manipulate atoms in semiconductor structures, as well how a suite of tools can be tied together in a cohesive simulation environment to take full advantage of the performance and capabilities in the latest nanometer processes.

Biography
Babak Taheri is the CEO at Silvaco Inc., a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).Babak was the recipient of ”the perfect project award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college.He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.

15:00 Near-Threshold Logic Benefits the Full Application Stack
  Lauri Koskinen, CTO and Co-founder, Minima
15:20
Deep Learning for Electronics Manufacturing
  Javier Cabello, Mycronic AB
Deep Learning for Electronics Manufacturing
Javier Cabello

Javier Cabello

Mycronic AB

Javier Cabello

Abstract
Deep learning is entering in the electronics manufacturing to further increase the reliability of its processes. In some cases, like in the operation of Pick & Place machines failures can only be afforded in a few cases per million operations.The combination of this high reliability requirement, autonomous decision making without intervention of human operators and a huge ever-growing flora of components to inspect present challenges to deploy deep learning in production systems. Particularly deep learning limited explain ability when the algorithms fail and the need to reduce also human involvement in supervised training schemas make it harder for this technology to arrive to the factory line.

Biography
Javier Cabello holds a degree in Computer Science and Engineering from Heriot-Watt University at Edinburgh. He is Lead Engineer for the computer vision group at Mycronic AB in Stockholm. He has being involved in developing several generations of machines within Pick & Place and Jetting technologies for the electronics manufacturing industry.

15:40
Cloud-Accelerated Innovation for Semiconductor Design and Verification
  David Pellerin, Head of WW Business Development, Hitech/Semiconductor, Amazon Web Services
Cloud-Accelerated Innovation for Semiconductor Design and Verification
David Pellerin

David Pellerin
Head of WW Business Development, Hitech/Semiconductor
Amazon Web Services

David Pellerin

Abstract
An explosion in the number and variety of intelligent edge devices, combined with cloud computing, are driving a need for more rapid innovation in semiconductor products. This talk presents examples and best-practices for cloud-accelerated semiconductor design and verification, including use-cases and examples inside and outside of Amazon. The talk will include an overview of how the development of next-generation products is enhanced through the use of cloud for scalable, high-throughput EDA flows. The talk will cover performance optimizations for computing, storage, and EDA workload orchestration, as well as covering how cloud enables secure collaboration in the semiconductor and electronics supply chain.

Biography
David Pellerin serves as Head of Worldwide Business Development for Hitech/Semiconductor at Amazon Web Services. Prior to joining AWS, Mr. Pellerin had a career in electronic design automation and hardware-accelerated reconfigurable computing. He has experience with digital logic simulation and optimization, high-level synthesis, grid and cluster computing, and embedded systems for image, video, and network processing. He has published five Prentice Hall technical books on EDA-related topics.

16:00 TBD
  Ian Campbell, CEO, OnScale
16:20
Addressing the "New-Space" Paradigm Shift in Development and Production of High Reliability, Space Grade Semiconductor Components
  Christian Sayer, Field Applications Engineer, Cobham Advanced Electronics Solutions
Addressing the "New-Space" Paradigm Shift in Development and Production of High Reliability, Space Grade Semiconductor Components
Christian Sayer

Christian Sayer
Field Applications Engineer
Cobham Advanced Electronics Solutions

Christian Sayer

Abstract
Semiconductor devices used for space missions have for decades dominated as specialized, radiation hardened components, built to the highest standards of reliability. Developed and manufactured in small quantities, the cost of traditional HighRel devices can exceed their commercial counterparts by several orders of magnitude.In recent years however, the number of smaller satellites, placed in lower orbits and designed for shorter operating lifetime, has increased. Especially the the concept of larger satellite constellations, with hundreds to thousands of spacecraft communicating with each other, covering the entire surface of the earth with a dense mesh of instruments or communication equipment for particular applications, have challenged the industry by their unconventional requirements. Cost of individual equipment becomes a primary factor for a mission involving a large number of spacecraft. New ways of designing for space need to be considered, questioning the traditional risk assessment.From the perspective of a traditional HighRel component supplier, what is our strategy to follow this shift from the "best possible" to the "good enough"? Looking at what impact a harsh environment can have on semiconductor devices, and what makes a space grade component flight-worthy, the LeanREL™ concept and line of products is introduced. Aiming to combine traditional space pedigree with a manufacturing flow substantially reducing cost, the technology is an enabler for lower orbit, shorter lifetime, high volume space missions.

Biography
Christian Sayer is Field Applications Engineer for Cobham Gaisler and Cobham Advanced Electronic Solutions. His focus is on processor, memory, interface, mixed signal and power components. Prior to Cobham, he worked as design and applications engineer for companies in the fabless semiconductor and embedded domain. Christian studied electrical engineering in Berlin, Montpellier and Paris. He holds a MSc. (Dipl.-Ing.) in Electrical Engineering of the Technical University of Berlin.

16:40 Panel discussion

Executive Panel: A Jim Hogan Fireside Chat: The Risk of Obsolete Design and Verification Environments in the RISC-V Era

Moderation Jim Hogan, Vista Ventures, LLC
Jim Hogan

Jim Hogan

Vista Ventures, LLC

Jim Hogan

Biography
James H. Hogan, executive managing partner of Vista Ventures, LLC, is an experienced senior executive who has worked in the semiconductor design and manufacturing industry for more than 40 years. He serves as a member of the board of directors for electronic system design, intellectual property, semiconductor equipment, material science and IT companies.Previously, Hogan was general partner at Telos Venture Partners and served as chief technology officer and senior vice president of business development at Cadence, and chief operating officer of Smart Machines, a semiconductor equipment automation company. Earlier, he worked for National Semiconductor and Philips where he established device physics laboratories globally and manufacturing yield improvement programs.Hogan founded Heart of Technology (HOT), a philanthropic organization based in San Jose, Calif., to unite the semiconductor industry to aid charities in their fundraising efforts for the betterment of local communities and enrichment of lives.He holds Bachelor of Arts and Math, Bachelor of Science and Computer Science and MBA degrees from San Jose State University.

Panelists
  • Gabriele Pulini, Sr. Business Development Manager, Mentor Graphics
  • Gabriele Pulini

    Gabriele Pulini
    Sr. Business Development Manager
    Mentor Graphics

    Gabriele Pulini

    Biography
    Gabriele Pulini joined Mentor in 1991 and has extensive engineering and marketing experience on the new technologies that changed over time the way new products are designed and brought to market. As part of the Emulation business unit within Mentor, a Siemens business, he is responsible for the new business opportunities, with today’s focus on self-driving and artificial intelligence applications.

  • Babak Taheri, CEO/CTO of Silvaco, Silvaco Inc
  • Babak Taheri

    Babak Taheri
    CEO/CTO of Silvaco
    Silvaco Inc

    Babak Taheri

    Biography
    Babak Taheri is the CEO at Silvaco Inc., a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).Babak was the recipient of ”the perfect project award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college.He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.

  • Paul Cunningham, Corporate Vice president and General Manager of the System Verification Group, Cadence Design Systems, Inc.
  • Paul Cunningham

    Paul Cunningham
    Corporate Vice president and General Manager of the System Verification Group
    Cadence Design Systems, Inc.

    Paul Cunningham

    Biography
    Paul Cunningham is corporate vice president and general manager of the system verification group at Cadence Design Systems. His product responsibilities include logic simulation, emulation, prototyping, formal, VIP, and debug. Prior to this, he was responsible for Cadence's frontend digital design tools including logic synthesis and design-for-test. Paul joined Cadence in 2011 through the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Paul holds a Master's Degree and a Ph.D. in Computer Science from the University of Cambridge, UK.

16:55 Panelists: Adnan Hamid, CEO, Breker Verification Systems; Calista Redmond, Chief Executive Officer, The RISC-V Foundation;
17:30

SEMI & ESDA Networking Hour